1. Field of the Invention
The present invention relates to a silicon die and, more particularly, to a hermetic seal for silicon die with a metal feed through structure.
2. Description of the Related Art
It is a common practice to permanently connect a silicon die to a semiconductor package. The package often has a multi-layered substrate with internal routing that provides an electrical connection between a number of package bonding pads on the top side of the package, and a number of pins or solder bumps on the bottom side of the package.
Inside the package, very fine bonding wires are used to provide an electrical connection between a number of die bonding pads on the top surface of the die, and the package bonding pads. The die bonding pads, in turn, are electrically connected to a semiconductor integrated circuit.
FIG. 1 shows a cross-sectional diagram that Illustrates a conventional ball grid array package 100. As shown in FIG. 1, package 100 includes a substrate 110 that has a top surface 112 and a bottom surface 114. Substrate 110 also has a number of housing bonding pads 116 that are formed on top surface 112, and a number of contact pads 120 that are formed on bottom surface 114. In addition, substrate 110 has a number of solder balls 122 that are attached to contact pads 120, and internal routing 124 that electrically connects the housing bonding pads 116 to the solder balls 122 via the contact pads 120. Solder balls 122, in turn, are shown connected to a printed circuit board 126.
As further shown in FIG. 1, package 100 also includes a die 130 that is attached to top surface 112 of substrate 110. Die 130, in turn, has a number of die bonding pads 132 that are electrically connected to a semiconductor integrated circuit. Package 100 additionally includes a number of very fine bonding wires 134 that connect the housing bonding pads 116 to the die bonding pads 132, and an encapsulant 136 formed over substrate 110 and die 130.
One advantage provided by package 100 is that the manufacturing process required to fabricate package 100 Is well known and understood. Package 100, however, suffers from a number of well-known disadvantages. One drawback to housing 100 is that, although the manufacturing process required to fabricate package 100 is well known and understood, package 100 is nonetheless costly to fabricate.
Another drawback to package 100 is that bonding wires 134 have additional inductance which, In turn, decreases the performance of the semiconductor integrated circuit. Thus, there is a need for a method of connecting a die to a semiconductor package that is less expensive than conventional approaches, and eliminates the need for bonding wires.
The present invention provides a die, and a method of forming the die, that substantially reduce the cost to connect the die to a semiconductor package, and eliminate the need for bonding wires. A semiconductor die formed in accordance with the present invention includes a semiconductor material that has a top surface, a bottom surface, and a plurality of edges. Each edge is connected to the top and bottom surfaces.
The die also includes a doped region that is formed in the top surface of the semiconductor material, and a layer of insulation material that is formed on the top surface of the semiconductor material. In addition, the die includes a first conductive contact that is formed through the layer of insulation material to make an electrical connection with the doped region, and a second conductive contact that is formed through the layer of isolation material and the semiconductor material. The second conductive contact extends from the bottom surface of the semiconductor material to the top surface of the layer of isolation material.
In addition, the die includes a first metal-1 trace and a second metal-1 trace. The first metal-1 trace is formed on the layer of insulation material and the first contact to make an electrical connection with the first contact. The second metal-1 trace is formed on the layer of insulation material and the second contact to make an electrical connection with the second contact.
The die further includes a layer of isolation material that is formed on the layer of insulation material, the first metal-1 trace, and the second metal-1 trace. The die additionally includes an edge protector that contacts and covers the edges.
The present invention also includes a method of processing a wafer. The wafer has a semiconductor material that has a top surface and a bottom surface. The wafer also has a doped region that is formed in the top surface of the semiconductor material, and a plurality of trench openings that are formed in the semiconductor material.
In addition, the wafer includes a layer of insulation material that is formed on the top surface of the semiconductor material. The layer of insulation material has a top surface, a first opening that exposes the doped region, and a plurality of second openings that expose the trench openings. The wafer further includes a first contact that is formed in the first opening, and a plurality of second contacts that are formed in the second openings and the trench openings.
The wafer additionally includes a first metal trace that is connected to the first contact, a second metal trace that is connected to the second contact, and a layer of passivation material that is formed over the layer of insulation material, the first metal trace, and the second metal trace.
The method Includes the steps of removing the bottom surface of the semiconductor material to expose the second contacts, and mounting the wafer on an adhesive material after the second contacts have been exposed. In addition, the method includes the step of cutting the wafer to form a plurality of first dice after the wafer has been mounted. The wafer has a plurality of first die-to-die openings with first widths. Each first die has a plurality of exposed edges.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.